Full chip integration tasks in modern Very Large System Integration (VLSI) commonly include integration of a digital part, an analog part, a power intent and software (SW) and are commonly performed in simulation. For the simulation, usually a real number model (RNM) of the analog part is used to increase simulation speed. In some cases the simulation speed is not fast enough to achieve the integration target, including cases like pre-silicon SW development with high interaction between the SW and the analog part, or cases like long algorithms that involve digital design (with or without SW) and analog design. The standard solution to accelerate simulation speed in these cases is to run on an emulator. However, emulators typically run synthesizable code only. Therefore, some approaches include manual conversion of analog emulation tools into synthesizable code compatible with digital emulation tools. These manual techniques are time consuming (up to several days or even weeks to complete a system level emulation), subjective, inaccurate, and difficult to generalize and re-use for different circuit configurations.
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